1. Field of the Invention
The present invention generally relates to a semiconductor device and a method for producing thereof, and more particularly to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface and a method for producing thereof.
2. Description of the Prior Art
Currently, with a need for small, thin, high-speed and high-performance electrical appliances, a demand for small, high-density and high-performance semiconductor devices is increasing. In order to respond to the demand, a QFP (Quad Flat Package) type semiconductor device and a QTP (Quad Tape-carrier Package) type semiconductor device have been gradually replaced by .mu.BGA-type semiconductors using BGA (Ball Grid Array) techniques or TAB (Tape Automated Bonding) techniques. Also, a reliability and electrical characteristics of the small-size semiconductor devices are desired to be improved.
Presently, a semiconductor device of a surface-package type is widely used in order to provided a high-density semiconductor device. In the QFP semiconductor devices of the surface-package type, a terminal has various shapes such as a gull-wing shape or a J-shape. The QFP semiconductor devices having a J-shaped terminal is called QFJ (Quad Flat J-Leaded Package). In the QFJ semiconductor device, BGA technique has been widely used, as described above.
FIG. 1 is a schematic illustration showing a QFJ-type semiconductor device. In the semiconductor device 10 shown in FIG. 1, leads (outer leads) 10b extend from four edges of the package 10a in which a semiconductor chip is molded. Each of the leads is bent in a J-shape. The semiconductor device 10 is mounted on the pattern of the substrate through solder.
FIGS. 2A and 2B are schematic illustrations showing a conventional .mu.BGA-package-type semiconductor device. FIG. 2A is a sectional view and FIG. 2B is a plan view.
In a semiconductor device 11 shown in FIGS. 2A and 2B, a prescribed number of pads 13 are provided on a semiconductor chip 12. On the semiconductor chip 12 except where the pads 13 are provided, an elastic adhesive 14 is applied. Around the semiconductor chip 12, a frame member 16 made of, for example, a metal, for protecting the semiconductor chip 12 and for releasing heat generated by the semiconductor chip 12, is secured through an adhesive 15a. An adhesive 15b is supplied on the frame member 16.
On the other hand, a pattern 18 of copper foil is provided on a resin film 17 of, for example, polyimide (PI). The pattern 18 comprises outer pads 18a and leads 18b extended from the outer pads 18a in order to constitute a TC (Tape Carrier) structure. Also, holes 19 are formed in the resin film 17 at positions corresponding to the outer pads 18a. In the holes 19, ball electrodes 20 of gold or solder connected to the outer pads 18a are provided in a lattice formation. A pitch of the ball electrodes is, for example, 0.5 mm. These ball electrodes 20 function as outer terminals.
The resin film 17 is bonded on the above-mentioned adhesive 14, 15b. The lead 18b extended from the pattern 18 is connected to the pads 13 of the semiconductor chip 12 by, for example, welding. These portions are sealed by a resin 15c of, for example, epoxy resin. The semiconductor device 11 is formed in the .mu.BGA package structure in which the ball electrodes 20 are provided in a size similar to the semiconductor chip size.
A flat size of the semiconductor device 11 is determined by the semiconductor chip size, a number of terminals and a terminal pitch.
That is, when an area determined by the number of the pads and the terminal pitch does not exceed an area of the semiconductor chip 12, the flat size of the semiconductor device 12 is determined by the pads provided on the semiconductor chip 12 being outside of the outer terminals arranged in a lattice formation.
On the contrary, when an area determined by the number of the pads and the terminal pitch exceeds the area of the semiconductor chip 12, the pads are not always outside of the outer terminal, and a flat area of the semiconductor device is determined by an area surrounded by the outer terminals arranged in a lattice formation.
However, in the semiconductor device 10 shown in FIG. 1, since the leads extend from the side faces of the package 10, the number of pins is limited and the production cost cannot be easily reduced.
Also, since the TAB method is used for the connection between the semiconductor chip 12 and the outer terminals, the semiconductor device 11 does not have a flexibility.
Also, when all the outer terminals are provided on the semiconductor chip 12, packing is difficult. For example, when more than 324 pins are provided, and a pitch for the pads is less than 80 .mu.m, a pitch for the outer terminals is required to be less than 0.4 mm. On the other hand, when a pitch for the outer terminals is more than 0.5 mm, the semiconductor chip 12 is required to be increased in size, and a total cost therefore becomes higher.
Also, since the outer terminals (bump electrodes 20) are required to be plated in a production of the semiconductor device 11, a cost for the production is increased.
Further, since a part of the semiconductor chip 12 is exposed in the conventional semiconductor device 11, a reliability thereof is lowered.